【ARM CoreLink 系列 5 -- CI-700 控制器介绍】

文章目录

- 1.1 什么是 CI-700？
- - 1.1.1 关于 CI-700
  - 1.1.2 CI-700 特点
- 1.2 全局配置参数
- - 1.2.1 寻址能力
- 1.3 组件和配置
- - 1.3.1 CI-700 互联的结构
  - 1.3.2 Crosspoint(XP)
  - 1.3.3 外部接口
- 1.4 组件(Components)
- - 1.4.1 RN-I & RN-D
  - 1.4.2 HN-F（Fully coherent Home Node）
  - 1.4.3 SBSX（AMBA 5 CHI to ACE5-Lite bridge）
  - 1.4.4 MTSX(Memory Tag Slave Interface)
- 1.5 System Address Map
- - 1.5.1 RN SAM
  - - 1.5.1.1 RN SAM memory regions and target types
    - 1.5.1.2 SAM memory region size configuration
    - 1.5.1.3 RN SAM target ID selection

上篇文章：ARM CoreLink 系列 4 – NIC-400 控制器详细介绍

1.1 什么是 CI-700？

CI-700是一种AMBA® 5 CHI互连，具有可定制的网状拓扑结构，采用 Armv9 处理器设计，可提供全面计算解决方案。它可以从主流智能手机扩展到高端智能手机，再到笔记本电脑级设备。设计与 CoreLink 网络互连和 CoreLink MMU-700 内存管理单元配对使用。
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图 1-1

1.1.1 关于 CI-700

Feature	Details
Designed and optimized for premium smartphones and laptops.	Based on high-performance AMBA CHI mesh interconnect technology Fully coherent interconnect supports from one to eight coherency clusters over AMBA CHI interface
High bandwidth and low latency from high frequency implementation	Supports low power implementations from 1GHz to high performance implementations up to 2GHz in 5nm processes
Configurable Unified System Level Cache	System level cache may be shared with GPU and other accelerators MPAM partitioning enables control of how System level cache resources are allocated and increases predictability Exclusive System level cache: data cached in the CPU cluster is not duplicated in the System level cache Snoop filter avoids the need to broadcast snoops to all CPU clusters Exclusive System level cache: data cached in the CPU cluster is not duplicated in the System level cache
Security	Adopts latest Armv9 architecture features Interface standards focus on security, performance, reliability, and virtualization Memory Tagging Extensions (MTE) for increased security AMBA CHI.E and AMBA AXI.H for Armv9 architecture, security, and virtualization support