Xilinx Vitis 2020工程源目录修改

1 背景

Xilinx Vitis可以做standalone程序开发,不过其工程中使用的路径为绝对路径。工程更换位置后编译将会显示错误。例如：源目录为D:/work,复制到同事电脑上放到C:/work(同事电脑只有一个C盘)。利用Vitis打开工程编译会有一堆错误，提示文件找不到。

2 分析

通过分析Vitis工程中有三个工程文件于路径相关:

xxx_system.sprj 其格式是一个xml文件,其中字段：
- platform 存放.xpfm文件
xxx.prj 其格式是一个xml文件，其中字段:
- platform 存放.xpfm文件
- location 存放xxx.prj文件路径
platform.spr 平台文件，其格式是json文件，其中字段:
- platHandOff 存放xsa文件路径
- qemuArgs 存放qemu_args.txt文件全路径，是Vitis配置文件，与Vitis安装位置有关。
- qemuData 存放qemu Data文件路径，与Vitis安装位置有关。

修改说明：

将以上文件路径根据新路径(C:/work)替换旧路径(D:/work)即可。
如果Vitis安装路径不同，需要更新qemuArgs和qemuData字段对应路径。

3 解决

可以通过手动修改以上文件是可以解决问题，不过手动修改容易出错误。更好的方式是写一脚本来做文件路径替换，这个脚本需要处理xml和json文件。Python语言内置xml和json库，是理想语言选择。
Python脚本如下：

import os
import json
import xml.etree.ElementTree as ETdef get_project_files(path):sprjfile = ""prjfile = ""sprfile = ""for root, _, files in os.walk(path):for file in files:_, ext = os.path.splitext(file)if ext == ".sprj":sprjfile = os.path.join(root, file)if ext == ".prj":prjfile = os.path.join(root, file)if ext == ".spr":sprfile = os.path.join(root, file)return (sprjfile, prjfile, sprfile)def get_file(path, filename):fullfilename = ""for root, _, files in os.walk(path):for file in files:if file == filename:fullfilename = os.path.join(root, file)breakreturn fullfilenamedef update_file(filename, value1, newvalue1, value2 = None, newvalue2 = None):file = open(filename, "r", encoding="ascii")fileData = file.read()file.close()fileData = fileData.replace(value1, newvalue1)print(value1, " => ", newvalue1)if value2 != None and newvalue2 != None:fileData = fileData.replace(value2, newvalue2)print(value2, " => ", newvalue2)file = open(filename, "w", encoding="ascii")file.write(fileData)file.close()def update_sprj(sprjfile, path):tree = ET.parse(sprjfile)attrib = tree.getroot().attribplatform = attrib.get("platform", "")filename = get_file(path, os.path.basename(platform))filename = filename.replace("\\", "/")update_file(sprjfile, platform, filename)def update_prj(prjfile, path):tree = ET.parse(prjfile)attrib = tree.getroot().attribplatform = attrib.get("platform", "")location = attrib.get("location", "")platform_filename = get_file(path, os.path.basename(platform))location_dirname = os.path.dirname(prjfile)platform_filename = platform_filename.replace("\\", "/")location_dirname = location_dirname.replace("\\", "/")update_file(prjfile, platform, platform_filename, location, location_dirname)def update_spr(sprfile, path, xilinx_qemu_path):file = open(sprfile, "r", encoding='utf-8')spr_data = json.load(file)file.close()platHandOff = spr_data.get("platHandOff", "")systems = spr_data.get("systems", {})platHandOff_filename = get_file(path + "\\board", os.path.basename(platHandOff))platHandOff_filename = platHandOff_filename.replace("\\", "/")update_file(sprfile, platHandOff, platHandOff_filename)if len(systems) == 1:domains = systems[0].get("domains", [])if len(domains) >= 2:qemuArgs = domains[1].get("qemuArgs", "")qemuData = domains[1].get("qemuData", "")update_file(sprfile, qemuData, xilinx_qemu_path)path = 'E:\\g\\work'
xilinx_qemu_path='D:/Xilinx/Vitis/2020.1/data/emulation/platforms/zynq/qemu/'
sprjfile, prjfile, sprfile = get_project_files(path)print("update file: ", sprjfile) # xml file
update_sprj(sprjfile, path)
print()print("update file: ", prjfile) # xml file
update_prj(prjfile, path)
print()print("update file: ", sprfile) # xml json
update_spr(sprfile, path, xilinx_qemu_path)

说明:

脚本需要两个参数：
- 工程所在路径的上一路径
- Xilinx的qemu路径
get_project_files 函数根据工程路径查找三个工程文件。
update_sprj 更新sprj文件
update_prj 更新prj文件
update_spr 更新platform.spr文件

4 使用

4.1 修改路径

E:/g/work路径如下：

.
├── board
└── workspace├── app_platform├── app└── app_system

说明：

board 文件夹存放xsa文件
workspace 为工程路径：
- app_platform 为平台路径
- app_system 为系统路径
- app 为应用路径

运行Python脚本

python3 patch.py
update file:  E:\g\work\workspace\app_system\app_system.sprj
X:/work/workspace/app_platform/export/app_platform/app_platform.xpfm  =>  E:/g/work/workspace/app_platform/export/app_platform/app_platform.xpfmupdate file:  E:\g\work\workspace\app\app.prj
X:/work/workspace/app_platform/export/app_platform/app_platform.xpfm  =>  E:/g/work/workspace/app_platform/export/app_platform/app_platform.xpfm
X:/work/workspace/app  =>  E:/g/work/workspace/appupdate file:  E:\g\work\workspace\app_platform\platform.spr
X:/work/board/app_platform_v1.0.xsa  =>  E:/g/work/board/app_platform_v1.0.xsa
C:/Xilinx/Vitis/2020.1/data/emulation/platforms/zynq/qemu/  =>  D:/Xilinx/Vitis/2020.1/data/emulation/platforms/zynq/qemu/

4.2 编译工程

4.2.1 清理工程

在这里插入图片描述

在上图中选择Clean菜单项，清理工程
在这里插入图片描述

如上图所示全部清理

buildplatform.bat 50156 app_platform clean 
XSDB Server Channel: tcfchan#10
Cleaning the zynq_fsbl application.
rm -rf  sd.o  nand.o  image_mover.o  md5.o  fsbl_hooks.o  main.o  nor.o  qspi.o  rsa.o  ps7_init.o  pcap.o  fsbl_handoff.o zynq
_fsbl_bsp/ps7_cortexa9_0/lib/libxil.a executable.elf *.oCleaning the zynq_fsbl application, bsp
make -C ps7_cortexa9_0/libsrc/bram_v4_4/src -s clean make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_7/src -s clean make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_9/src -s clean make -C ps7_cortexa9_0/libsrc/ddrps_v1_1/src -s clean rm -f ps7_cortexa9_0/lib/libxil.aCleaning the BSP for domain  - domain_ps7_cortexa9_0
make -C ps7_cortexa9_0/libsrc/bram_v4_4/src -s clean make -C ps7_cortexa9_0/libsrc/uartps_v3_9/src -s clean make -C ps7_cortexa9_0/libsrc/xadcps_v2_4/src -s clean make -C ps7_cortexa9_0/libsrc/xilffs_v4_3/src -s clean rm -f ps7_cortexa9_0/lib/libxil.a16:22:11 Build Finished (took 2s.891ms)

4.2.2 编译工程

在这里插入图片描述
在上图选择Build All菜单项编译工程

Generating bif file for the system project
generate_system_bif.bat 50156 E:/g/work/workspace/app_platform/export/app_platform/app_platform.xpfm domain_ps7_cortexa9_0 E:/g/work/workspace/app_system/Debug/system.bif
sdcard_gen --xpfm E:/g/work/workspace/app_platform/export/app_platform/app_platform.xpfm --sys_config app_platform --bif E:/g/work/workspace/app_system/Debug/system.bif --bitstream E:/g/work/workspace/app/_ide/bitstream/app_loadboardNI_v1.0.bit --elf E:/g/work/workspace/app/Debug/app.elf,ps7_cortexa9_0
creating BOOT.BIN using E:/g/work/workspace/app/_ide/bitstream/app_loadboardNI_v1.0.bit 
Running D:/Xilinx/Vitis/2020.1/bin/bootgen  -image E:/g/work/workspace/app_system/Debug/sd_card_temp/boot.bif -w -o i BOOT.BIN16:25:54 Build Finished (took 5s.226ms)