名称:DDS信号发生器波形发生器
软件:Quartus
语言:VHDL
要求:
在EDA平台中使用VHDL语言为工具,设计一个常见信号发生电路,要求:
1. 能够产生锯齿波,方波,三角波,正弦波共四种信号;
2. 信号的频率和幅度可以通过按键调节;
3. 采用模块化设计,包含但不局限于:调频模块,调幅模块,波形的选择与切换模块等;
代码下载:DDS信号发生器波形发生器VHDL_Verilog/VHDL资源下载
代码网:hdlcode.com
部分代码展示
LIBRARY ieee;USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; --DDS频率等于clk*N/2^13,clk为输入时钟,N为频率控制字frequency;2^13是因为ROM里面存储了8192个点,相位累加器位宽为13位 ENTITY DDS_top ISPORT (clk_in : IN STD_LOGIC;--时钟 rst_p: IN STD_LOGIC;--复位wave_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);--01输出sin,10输出方波,11输出三角波,00锯齿frequency_key : IN STD_LOGIC;--频率控制按键amplitude_key : IN STD_LOGIC;--幅值控制按键 wave : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)--输出波形); END DDS_top; ARCHITECTURE behave OF DDS_top IS --例化模块 --波形选择模块COMPONENT wave_sel ISPORT (clk_in : IN STD_LOGIC;wave_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);douta_fangbo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);douta_sanjiao : IN STD_LOGIC_VECTOR(7 DOWNTO 0);douta_sin : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta_juchi : IN STD_LOGIC_VECTOR(7 DOWNTO 0);wave : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));END COMPONENT;--相位累加器模块COMPONENT Frequency_ctrl ISPORT (clk_in : IN STD_LOGIC;frequency : IN STD_LOGIC_VECTOR(9 DOWNTO 0);addra : OUT STD_LOGIC_VECTOR(12 DOWNTO 0));END COMPONENT; --ROM表 COMPONENT sin_ROM IS PORT ( address: IN STD_LOGIC_VECTOR (12 DOWNTO 0); clock: IN STD_LOGIC := '1'; q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; --ROM表 COMPONENT fangbo_ROM IS PORT ( address: IN STD_LOGIC_VECTOR (12 DOWNTO 0); clock: IN STD_LOGIC := '1'; q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; --ROM表 COMPONENT sanjiao_ROM IS PORT ( address: IN STD_LOGIC_VECTOR (12 DOWNTO 0); clock: IN STD_LOGIC := '1'; q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; --ROM表 COMPONENT juchi_ROM IS PORT ( address: IN STD_LOGIC_VECTOR (12 DOWNTO 0); clock: IN STD_LOGIC := '1'; q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; --按键频率控制 COMPONENT Frequency_add ISPORT (clk_in : IN STD_LOGIC;rst_p : IN STD_LOGIC;frequency_key : IN STD_LOGIC;frequency : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)--频率控制字,10位位宽,变化范围可以为1~1000); END COMPONENT; --按键幅值控制 COMPONENT amplitude_add ISPORT (clk_in : IN STD_LOGIC;rst_p : IN STD_LOGIC;amplitude_key : IN STD_LOGIC;amplitude : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)--幅值); END COMPONENT;SIGNAL addra : STD_LOGIC_VECTOR(12 DOWNTO 0);SIGNAL douta_fangbo : STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL douta_sanjiao : STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL douta_sin : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL douta_juchi : STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL wave_temp : STD_LOGIC_VECTOR(7 DOWNTO 0);--波形SIGNAL frequency : STD_LOGIC_VECTOR(9 DOWNTO 0);--频率控制字,控制输出波形频率,值越大,频率越大SIGNAL amplitude : STD_LOGIC_VECTOR(7 DOWNTO 0);--幅值控制字,值越大,幅值越大 BEGIN --按键频率控制 i_Frequency_add: Frequency_addPORT MAP(clk_in => clk_in,rst_p => rst_p,frequency_key => frequency_key,frequency => frequency--频率控制字,10位位宽,变化范围可以为1~1000); --按键幅值控制 i_amplitude_add: amplitude_addPORT MAP(clk_in => clk_in,rst_p => rst_p,amplitude_key => amplitude_key,amplitude => amplitude--幅值控制字);--方波ROM,存储波形数据i_fangbo_ROM : fangbo_ROMPORT MAP (clock => clk_in,address => addra,q => douta_fangbo);--三角波ROM,存储波形数据i_sanjiao_ROM : sanjiao_ROMPORT MAP (clock => clk_in,address => addra,q => douta_sanjiao);--sin波ROM,存储波形数据i_sin_ROM : sin_ROMPORT MAP (clock => clk_in,address => addra,q => douta_sin);--锯齿波ROM,存储波形数据i_juchi_ROM : juchi_ROMPORT MAP (clock => clk_in,address => addra,q => douta_juchi);--相位累加器i_Frequency_ctrl : Frequency_ctrlPORT MAP (clk_in => clk_in,frequency => frequency,--频率控制字addra => addra--输出地址);--波形选择控制i_wave_sel : wave_selPORT MAP (clk_in => clk_in,wave_select => wave_select,--01输出sin,10输出方波,11输出三角波douta_fangbo => douta_fangbo,--方波douta_sanjiao => douta_sanjiao,--三角douta_sin => douta_sin,--正弦 douta_juchi => douta_juchi,--锯齿wave => wave_temp--输出波形 );wave<=wave_temp*amplitude;--波形乘以幅值 END behave;
设计文档(文档点击可下载):
设计文档.doc
DDS原理
1. 工程文件
2. 程序文件
ROM IP核
3. 程序编译
4. RTL图
5. Testbench
6. 仿真图
整体仿真图
相位累加器模块
波形选择模块
正弦波ROM模块
三角波ROM模块
方波ROM模块
锯齿波ROM模块
按键控制频率信号模块
按键控制幅值信号模块