随便记录一下下：

Cordic IP核使用说明以及避坑记录-CSDN博客

本次只用到了Translate，记录一下自己遇到的坑坑

实际配置：

`timescale 1ns / 1nsmodule cordic_tb();reg clk;wire m_axis_dout_tvalid;reg s_axis_cartesian_tvalid = 0;wire [31 : 0] s_axis_cartesian_tdata;wire [31 : 0] m_axis_dout_tdata;wire [15:0] x_abs   = m_axis_dout_tdata[15:0];  //abs(15:0) fix16_14; wire [15:0] x_phase = m_axis_dout_tdata[31:16]; //Phase(31:16) fix16_13;reg [15:0] x_r = 0;reg [15:0] x_i = 0;always #10 clk = ~clk;reg [5:0] cnt ;reg [1:0] index;always@(posedge clk) if(cnt==22) begin cnt <= 0;  index <= index + 1;endelse    cnt <= cnt + 1;always@(posedge clk) case (index)2'b00: begin x_r <= 16'b0011_0000_0000_0000; x_i <= 16'b0011_0000_0000_0000; end //fix16_14   0.75+0.75i    12'b01: begin x_r <=~16'b0100_0000_0000_0000 + 1'b1; x_i <= 16'b0011_0000_0000_0000; end //fix16_14   -1+0.75i   22'b10:begin x_r <=~16'b0001_0000_0000_0000 + 1'b1; x_i <=~16'b0010_0000_0000_0000 + 1'b1; end //fix16_14   -0.25-0.5i  32'b11: begin x_r <= 16'b0001_0000_0000_0000; x_i <=~16'b0010_1000_0000_0000 + 1'b1; end //fix16_14   0.25-0.625i   4endcaseassign s_axis_cartesian_tdata = {x_i, x_r}; initial beginclk = 0;index = 0;cnt = 0 ;index = 0 ;s_axis_cartesian_tvalid <= 0;#100 s_axis_cartesian_tvalid <= 1;end    cordic_translate cordic_ (.aclk(clk),                                        // input wire aclk.s_axis_cartesian_tvalid(s_axis_cartesian_tvalid),  // input wire s_axis_cartesian_tvalid.s_axis_cartesian_tdata(s_axis_cartesian_tdata),    // input wire [31 : 0] s_axis_cartesian_tdata.m_axis_dout_tvalid(m_axis_dout_tvalid),            // output wire m_axis_dout_tvalid.m_axis_dout_tdata(m_axis_dout_tdata)              // output wire [31 : 0] m_axis_dout_tdata  );    //input  Real(15:0) fix16_14; Imag(31:16) fix16_14//output Real(15:0) fix16_14; Phase(31:16) fix16_13 endmodule

// 调试后还是比较简单捏~