`timescale 1ns/1nsparameter CLOCK_FREQ = 100_000;
parameter LED_ON_PERIOD = 2*CLOCK_FREQ;
parameter LED_OFF_PERIOD = 18*CLOCK_FREQ; module motor
(input pll_inst1_CLKOUT0,input pll_inst1_LOCKED,output led,output pwm0,output pwm1,output pwm2,output pwm3,output pwm4,output pwm5
);wire clk_ref = pll_inst1_CLKOUT0;
wire sys_rst_n = pll_inst1_LOCKED;reg [31:0] counter;
reg led_state;always @(posedge clk_ref or negedge sys_rst_n) beginif (!sys_rst_n) begincounter <= 0;led_state <= 0;end else begincounter <= counter + 1;if (counter < LED_ON_PERIOD) beginled_state <= 1;end else if (counter < LED_ON_PERIOD + LED_OFF_PERIOD) beginled_state <= 0;end else begincounter <= 0;endend
endassign led = led_state;
assign pwm0 = led_state;
assign pwm1 = led_state;
assign pwm2 = led_state;
assign pwm3 = led_state;
assign pwm4 = led_state;
assign pwm5 = led_state;endmodule
- 直接分配占空比失败 改成了闪烁的逻辑
- 尽量先用简单逻辑试一试 参考案例较少
- 注意再xilinx里面 pwm等历程比较丰富 但是尽量少调用ip包 (那种黑箱太多的 尤其ai类)
- fpga尽量verliog逻辑走 目前尽量不要复杂逻辑 尤其复杂通信算法(用了要确保时序 注意) 但是通信相关的数据吞吐非常好