由于对于FPGA+NIOS II 的工作需要,对工作过程中遇到的问题进行记录,持续更新。
1、BSP directory does not exist: . Stop.
Nios II使用过程中遇到的一些问题2_error executing 'nios2-bsp-generate-files --bsp-di-CSDN博客https://blog.csdn.net/qq_39485231/article/details/105908579
2、ignored dangling comma in List of Port Connections
Warning (10275): Verilog HDL Module Instantiation warning at xxx.v(24): ignored dangling comma in List of Port Connections
---- 例化模块多了 逗号,去除最后一个逗号;
3、Error (12007): Top-level design entity "xxx" is undefined
模块名xxx.v与顶层实体名module xxx不一致;
4、output or inout port "xxx" must be connected to a structural net expression
Error (10663): Verilog HDL Port Connection error at top.v(70): output or inout port "trip_signal" must be connected to a structural net expression
module protection_top(input sys_clk, //时钟input sys_rst_n, //复位,低电平有效input [3:0] avl_address, //地址input avl_write, //写请求input [31:0] avl_writedata, //写数据input avl_read, //读请求output [31:0] avl_readdata, //读数据output reg trip_irq
);///<output reg trip_irq 应使用wiwe