error: #5: cannot open source input file “core_cmInstr.h“

GD32F103VET6和STM32F103VET6引脚兼容。

GD32F103VET6工程模板需要包含头文件：core_cmInstr.h和core_cmFunc.h，这个和STM32F103还是有区别的，否则会报错，如下：

 error:  #5: cannot open source input file "core_cmInstr.h": No such file or directory

贴出来，以便大家去下载，还要积分，找得还辛苦。

/**************************************************************************//*** @file     core_cmFunc.h* @brief    CMSIS Cortex-M Core Function Access Header File* @version  V3.02* @date     24. May 2012** @note* Copyright (C) 2009-2012 ARM Limited. All rights reserved.** @par* ARM Limited (ARM) is supplying this software for use with Cortex-M* processor based microcontrollers.  This file can be freely distributed* within development tools that are supporting such ARM based processors.** @par* THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.*******************************************************************************/#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H/* ###########################  Core Function Access  ########################### */
/** \ingroup  CMSIS_Core_FunctionInterface\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions@{*/#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */#if (__ARMCC_VERSION < 400677)#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif/* intrinsic void __enable_irq();     */
/* intrinsic void __disable_irq();    *//** \brief  Get Control RegisterThis function returns the content of the Control Register.\return               Control Register value*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{register uint32_t __regControl         __ASM("control");return(__regControl);
}/** \brief  Set Control RegisterThis function writes the given value to the Control Register.\param [in]    control  Control Register value to set*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{register uint32_t __regControl         __ASM("control");__regControl = control;
}/** \brief  Get IPSR RegisterThis function returns the content of the IPSR Register.\return               IPSR Register value*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{register uint32_t __regIPSR          __ASM("ipsr");return(__regIPSR);
}/** \brief  Get APSR RegisterThis function returns the content of the APSR Register.\return               APSR Register value*/
__STATIC_INLINE uint32_t __get_APSR(void)
{register uint32_t __regAPSR          __ASM("apsr");return(__regAPSR);
}/** \brief  Get xPSR RegisterThis function returns the content of the xPSR Register.\return               xPSR Register value*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{register uint32_t __regXPSR          __ASM("xpsr");return(__regXPSR);
}/** \brief  Get Process Stack PointerThis function returns the current value of the Process Stack Pointer (PSP).\return               PSP Register value*/
__STATIC_INLINE uint32_t __get_PSP(void)
{register uint32_t __regProcessStackPointer  __ASM("psp");return(__regProcessStackPointer);
}/** \brief  Set Process Stack PointerThis function assigns the given value to the Process Stack Pointer (PSP).\param [in]    topOfProcStack  Process Stack Pointer value to set*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{register uint32_t __regProcessStackPointer  __ASM("psp");__regProcessStackPointer = topOfProcStack;
}/** \brief  Get Main Stack PointerThis function returns the current value of the Main Stack Pointer (MSP).\return               MSP Register value*/
__STATIC_INLINE uint32_t __get_MSP(void)
{register uint32_t __regMainStackPointer     __ASM("msp");return(__regMainStackPointer);
}/** \brief  Set Main Stack PointerThis function assigns the given value to the Main Stack Pointer (MSP).\param [in]    topOfMainStack  Main Stack Pointer value to set*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{register uint32_t __regMainStackPointer     __ASM("msp");__regMainStackPointer = topOfMainStack;
}/** \brief  Get Priority MaskThis function returns the current state of the priority mask bit from the Priority Mask Register.\return               Priority Mask value*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{register uint32_t __regPriMask         __ASM("primask");return(__regPriMask);
}/** \brief  Set Priority MaskThis function assigns the given value to the Priority Mask Register.\param [in]    priMask  Priority Mask*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{register uint32_t __regPriMask         __ASM("primask");__regPriMask = (priMask);
}#if       (__CORTEX_M >= 0x03)/** \brief  Enable FIQThis function enables FIQ interrupts by clearing the F-bit in the CPSR.Can only be executed in Privileged modes.*/
#define __enable_fault_irq                __enable_fiq/** \brief  Disable FIQThis function disables FIQ interrupts by setting the F-bit in the CPSR.Can only be executed in Privileged modes.*/
#define __disable_fault_irq               __disable_fiq/** \brief  Get Base PriorityThis function returns the current value of the Base Priority register.\return               Base Priority register value*/
__STATIC_INLINE uint32_t  __get_BASEPRI(void)
{register uint32_t __regBasePri         __ASM("basepri");return(__regBasePri);
}/** \brief  Set Base PriorityThis function assigns the given value to the Base Priority register.\param [in]    basePri  Base Priority value to set*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{register uint32_t __regBasePri         __ASM("basepri");__regBasePri = (basePri & 0xff);
}/** \brief  Get Fault MaskThis function returns the current value of the Fault Mask register.\return               Fault Mask register value*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{register uint32_t __regFaultMask       __ASM("faultmask");return(__regFaultMask);
}/** \brief  Set Fault MaskThis function assigns the given value to the Fault Mask register.\param [in]    faultMask  Fault Mask value to set*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{register uint32_t __regFaultMask       __ASM("faultmask");__regFaultMask = (faultMask & (uint32_t)1);
}#endif /* (__CORTEX_M >= 0x03) */#if       (__CORTEX_M == 0x04)/** \brief  Get FPSCRThis function returns the current value of the Floating Point Status/Control register.\return               Floating Point Status/Control register value*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)register uint32_t __regfpscr         __ASM("fpscr");return(__regfpscr);
#elsereturn(0);
#endif
}/** \brief  Set FPSCRThis function assigns the given value to the Floating Point Status/Control register.\param [in]    fpscr  Floating Point Status/Control value to set*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)register uint32_t __regfpscr         __ASM("fpscr");__regfpscr = (fpscr);
#endif
}#endif /* (__CORTEX_M == 0x04) */#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */#include <cmsis_iar.h>#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */#include <cmsis_ccs.h>#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions *//** \brief  Enable IRQ InterruptsThis function enables IRQ interrupts by clearing the I-bit in the CPSR.Can only be executed in Privileged modes.*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{__ASM volatile ("cpsie i" : : : "memory");
}/** \brief  Disable IRQ InterruptsThis function disables IRQ interrupts by setting the I-bit in the CPSR.Can only be executed in Privileged modes.*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{__ASM volatile ("cpsid i" : : : "memory");
}/** \brief  Get Control RegisterThis function returns the content of the Control Register.\return               Control Register value*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{uint32_t result;__ASM volatile ("MRS %0, control" : "=r" (result) );return(result);
}/** \brief  Set Control RegisterThis function writes the given value to the Control Register.\param [in]    control  Control Register value to set*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{__ASM volatile ("MSR control, %0" : : "r" (control) );
}/** \brief  Get IPSR RegisterThis function returns the content of the IPSR Register.\return               IPSR Register value*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{uint32_t result;__ASM volatile ("MRS %0, ipsr" : "=r" (result) );return(result);
}/** \brief  Get APSR RegisterThis function returns the content of the APSR Register.\return               APSR Register value*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{uint32_t result;__ASM volatile ("MRS %0, apsr" : "=r" (result) );return(result);
}/** \brief  Get xPSR RegisterThis function returns the content of the xPSR Register.\return               xPSR Register value*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{uint32_t result;__ASM volatile ("MRS %0, xpsr" : "=r" (result) );return(result);
}/** \brief  Get Process Stack PointerThis function returns the current value of the Process Stack Pointer (PSP).\return               PSP Register value*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{register uint32_t result;__ASM volatile ("MRS %0, psp\n"  : "=r" (result) );return(result);
}/** \brief  Set Process Stack PointerThis function assigns the given value to the Process Stack Pointer (PSP).\param [in]    topOfProcStack  Process Stack Pointer value to set*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
}/** \brief  Get Main Stack PointerThis function returns the current value of the Main Stack Pointer (MSP).\return               MSP Register value*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{register uint32_t result;__ASM volatile ("MRS %0, msp\n" : "=r" (result) );return(result);
}/** \brief  Set Main Stack PointerThis function assigns the given value to the Main Stack Pointer (MSP).\param [in]    topOfMainStack  Main Stack Pointer value to set*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
}/** \brief  Get Priority MaskThis function returns the current state of the priority mask bit from the Priority Mask Register.\return               Priority Mask value*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{uint32_t result;__ASM volatile ("MRS %0, primask" : "=r" (result) );return(result);
}/** \brief  Set Priority MaskThis function assigns the given value to the Priority Mask Register.\param [in]    priMask  Priority Mask*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}#if       (__CORTEX_M >= 0x03)/** \brief  Enable FIQThis function enables FIQ interrupts by clearing the F-bit in the CPSR.Can only be executed in Privileged modes.*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{__ASM volatile ("cpsie f" : : : "memory");
}/** \brief  Disable FIQThis function disables FIQ interrupts by setting the F-bit in the CPSR.Can only be executed in Privileged modes.*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{__ASM volatile ("cpsid f" : : : "memory");
}/** \brief  Get Base PriorityThis function returns the current value of the Base Priority register.\return               Base Priority register value*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{uint32_t result;__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );return(result);
}/** \brief  Set Base PriorityThis function assigns the given value to the Base Priority register.\param [in]    basePri  Base Priority value to set*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}/** \brief  Get Fault MaskThis function returns the current value of the Fault Mask register.\return               Fault Mask register value*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{uint32_t result;__ASM volatile ("MRS %0, faultmask" : "=r" (result) );return(result);
}/** \brief  Set Fault MaskThis function assigns the given value to the Fault Mask register.\param [in]    faultMask  Fault Mask value to set*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}#endif /* (__CORTEX_M >= 0x03) */#if       (__CORTEX_M == 0x04)/** \brief  Get FPSCRThis function returns the current value of the Floating Point Status/Control register.\return               Floating Point Status/Control register value*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)uint32_t result;__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );return(result);
#elsereturn(0);
#endif
}/** \brief  Set FPSCRThis function assigns the given value to the Floating Point Status/Control register.\param [in]    fpscr  Floating Point Status/Control value to set*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
#endif
}#endif /* (__CORTEX_M == 0x04) */#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions *//** The CMSIS functions have been implemented as intrinsics in the compiler.* Please use "carm -?i" to get an up to date list of all instrinsics,* Including the CMSIS ones.*/#endif/*@} end of CMSIS_Core_RegAccFunctions */#endif /* __CORE_CMFUNC_H */
/**************************************************************************//*** @file     core_cmInstr.h* @brief    CMSIS Cortex-M Core Instruction Access Header File* @version  V3.02* @date     08. May 2012** @note* Copyright (C) 2009-2012 ARM Limited. All rights reserved.** @par* ARM Limited (ARM) is supplying this software for use with Cortex-M* processor based microcontrollers.  This file can be freely distributed* within development tools that are supporting such ARM based processors.** @par* THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.*******************************************************************************/#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H/* ##########################  Core Instruction Access  ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction InterfaceAccess to dedicated instructions@{
*/#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */#if (__ARMCC_VERSION < 400677)#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif/** \brief  No OperationNo Operation does nothing. This instruction can be used for code alignment purposes.*/
#define __NOP                             __nop/** \brief  Wait For InterruptWait For Interrupt is a hint instruction that suspends executionuntil one of a number of events occurs.*/
#define __WFI                             __wfi/** \brief  Wait For EventWait For Event is a hint instruction that permits the processor to entera low-power state until one of a number of events occurs.*/
#define __WFE                             __wfe/** \brief  Send EventSend Event is a hint instruction. It causes an event to be signaled to the CPU.*/
#define __SEV                             __sev/** \brief  Instruction Synchronization BarrierInstruction Synchronization Barrier flushes the pipeline in the processor,so that all instructions following the ISB are fetched from cache ormemory, after the instruction has been completed.*/
#define __ISB()                           __isb(0xF)/** \brief  Data Synchronization BarrierThis function acts as a special kind of Data Memory Barrier.It completes when all explicit memory accesses before this instruction complete.*/
#define __DSB()                           __dsb(0xF)/** \brief  Data Memory BarrierThis function ensures the apparent order of the explicit memory operations beforeand after the instruction, without ensuring their completion.*/
#define __DMB()                           __dmb(0xF)/** \brief  Reverse byte order (32 bit)This function reverses the byte order in integer value.\param [in]    value  Value to reverse\return               Reversed value*/
#define __REV                             __rev/** \brief  Reverse byte order (16 bit)This function reverses the byte order in two unsigned short values.\param [in]    value  Value to reverse\return               Reversed value*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{rev16 r0, r0bx lr
}
#endif/** \brief  Reverse byte order in signed short valueThis function reverses the byte order in a signed short value with sign extension to integer.\param [in]    value  Value to reverse\return               Reversed value*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{revsh r0, r0bx lr
}
#endif/** \brief  Rotate Right in unsigned value (32 bit)This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\param [in]    value  Value to rotate\param [in]    value  Number of Bits to rotate\return               Rotated value*/
#define __ROR                             __ror#if       (__CORTEX_M >= 0x03)/** \brief  Reverse bit order of valueThis function reverses the bit order of the given value.\param [in]    value  Value to reverse\return               Reversed value*/
#define __RBIT                            __rbit/** \brief  LDR Exclusive (8 bit)This function performs a exclusive LDR command for 8 bit value.\param [in]    ptr  Pointer to data\return             value of type uint8_t at (*ptr)*/
#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))/** \brief  LDR Exclusive (16 bit)This function performs a exclusive LDR command for 16 bit values.\param [in]    ptr  Pointer to data\return        value of type uint16_t at (*ptr)*/
#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))/** \brief  LDR Exclusive (32 bit)This function performs a exclusive LDR command for 32 bit values.\param [in]    ptr  Pointer to data\return        value of type uint32_t at (*ptr)*/
#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))/** \brief  STR Exclusive (8 bit)This function performs a exclusive STR command for 8 bit values.\param [in]  value  Value to store\param [in]    ptr  Pointer to location\return          0  Function succeeded\return          1  Function failed*/
#define __STREXB(value, ptr)              __strex(value, ptr)/** \brief  STR Exclusive (16 bit)This function performs a exclusive STR command for 16 bit values.\param [in]  value  Value to store\param [in]    ptr  Pointer to location\return          0  Function succeeded\return          1  Function failed*/
#define __STREXH(value, ptr)              __strex(value, ptr)/** \brief  STR Exclusive (32 bit)This function performs a exclusive STR command for 32 bit values.\param [in]  value  Value to store\param [in]    ptr  Pointer to location\return          0  Function succeeded\return          1  Function failed*/
#define __STREXW(value, ptr)              __strex(value, ptr)/** \brief  Remove the exclusive lockThis function removes the exclusive lock which is created by LDREX.*/
#define __CLREX                           __clrex/** \brief  Signed SaturateThis function saturates a signed value.\param [in]  value  Value to be saturated\param [in]    sat  Bit position to saturate to (1..32)\return             Saturated value*/
#define __SSAT                            __ssat/** \brief  Unsigned SaturateThis function saturates an unsigned value.\param [in]  value  Value to be saturated\param [in]    sat  Bit position to saturate to (0..31)\return             Saturated value*/
#define __USAT                            __usat/** \brief  Count leading zerosThis function counts the number of leading zeros of a data value.\param [in]  value  Value to count the leading zeros\return             number of leading zeros in value*/
#define __CLZ                             __clz#endif /* (__CORTEX_M >= 0x03) */#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */#include <cmsis_iar.h>#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */#include <cmsis_ccs.h>#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions *//** \brief  No OperationNo Operation does nothing. This instruction can be used for code alignment purposes.*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{__ASM volatile ("nop");
}/** \brief  Wait For InterruptWait For Interrupt is a hint instruction that suspends executionuntil one of a number of events occurs.*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{__ASM volatile ("wfi");
}/** \brief  Wait For EventWait For Event is a hint instruction that permits the processor to entera low-power state until one of a number of events occurs.*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{__ASM volatile ("wfe");
}/** \brief  Send EventSend Event is a hint instruction. It causes an event to be signaled to the CPU.*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{__ASM volatile ("sev");
}/** \brief  Instruction Synchronization BarrierInstruction Synchronization Barrier flushes the pipeline in the processor,so that all instructions following the ISB are fetched from cache ormemory, after the instruction has been completed.*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{__ASM volatile ("isb");
}/** \brief  Data Synchronization BarrierThis function acts as a special kind of Data Memory Barrier.It completes when all explicit memory accesses before this instruction complete.*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{__ASM volatile ("dsb");
}/** \brief  Data Memory BarrierThis function ensures the apparent order of the explicit memory operations beforeand after the instruction, without ensuring their completion.*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{__ASM volatile ("dmb");
}/** \brief  Reverse byte order (32 bit)This function reverses the byte order in integer value.\param [in]    value  Value to reverse\return               Reversed value*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{uint32_t result;__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );return(result);
}/** \brief  Reverse byte order (16 bit)This function reverses the byte order in two unsigned short values.\param [in]    value  Value to reverse\return               Reversed value*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{uint32_t result;__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );return(result);
}/** \brief  Reverse byte order in signed short valueThis function reverses the byte order in a signed short value with sign extension to integer.\param [in]    value  Value to reverse\return               Reversed value*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{uint32_t result;__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );return(result);
}/** \brief  Rotate Right in unsigned value (32 bit)This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\param [in]    value  Value to rotate\param [in]    value  Number of Bits to rotate\return               Rotated value*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{__ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );return(op1);
}#if       (__CORTEX_M >= 0x03)/** \brief  Reverse bit order of valueThis function reverses the bit order of the given value.\param [in]    value  Value to reverse\return               Reversed value*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{uint32_t result;__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );return(result);
}/** \brief  LDR Exclusive (8 bit)This function performs a exclusive LDR command for 8 bit value.\param [in]    ptr  Pointer to data\return             value of type uint8_t at (*ptr)*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{uint8_t result;__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );return(result);
}/** \brief  LDR Exclusive (16 bit)This function performs a exclusive LDR command for 16 bit values.\param [in]    ptr  Pointer to data\return        value of type uint16_t at (*ptr)*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{uint16_t result;__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );return(result);
}/** \brief  LDR Exclusive (32 bit)This function performs a exclusive LDR command for 32 bit values.\param [in]    ptr  Pointer to data\return        value of type uint32_t at (*ptr)*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{uint32_t result;__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );return(result);
}/** \brief  STR Exclusive (8 bit)This function performs a exclusive STR command for 8 bit values.\param [in]  value  Value to store\param [in]    ptr  Pointer to location\return          0  Function succeeded\return          1  Function failed*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{uint32_t result;__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );return(result);
}/** \brief  STR Exclusive (16 bit)This function performs a exclusive STR command for 16 bit values.\param [in]  value  Value to store\param [in]    ptr  Pointer to location\return          0  Function succeeded\return          1  Function failed*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{uint32_t result;__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );return(result);
}/** \brief  STR Exclusive (32 bit)This function performs a exclusive STR command for 32 bit values.\param [in]  value  Value to store\param [in]    ptr  Pointer to location\return          0  Function succeeded\return          1  Function failed*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{uint32_t result;__ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );return(result);
}/** \brief  Remove the exclusive lockThis function removes the exclusive lock which is created by LDREX.*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{__ASM volatile ("clrex");
}/** \brief  Signed SaturateThis function saturates a signed value.\param [in]  value  Value to be saturated\param [in]    sat  Bit position to saturate to (1..32)\return             Saturated value*/
#define __SSAT(ARG1,ARG2) \
({                          \uint32_t __RES, __ARG1 = (ARG1); \__ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \__RES; \})/** \brief  Unsigned SaturateThis function saturates an unsigned value.\param [in]  value  Value to be saturated\param [in]    sat  Bit position to saturate to (0..31)\return             Saturated value*/
#define __USAT(ARG1,ARG2) \
({                          \uint32_t __RES, __ARG1 = (ARG1); \__ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \__RES; \})/** \brief  Count leading zerosThis function counts the number of leading zeros of a data value.\param [in]  value  Value to count the leading zeros\return             number of leading zeros in value*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{uint8_t result;__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );return(result);
}#endif /* (__CORTEX_M >= 0x03) */#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions *//** The CMSIS functions have been implemented as intrinsics in the compiler.* Please use "carm -?i" to get an up to date list of all intrinsics,* Including the CMSIS ones.*/#endif/*@}*/ /* end of group CMSIS_Core_InstructionInterface */#endif /* __CORE_CMINSTR_H */

 

本文来自互联网用户投稿，该文观点仅代表作者本人，不代表本站立场。本站仅提供信息存储空间服务，不拥有所有权，不承担相关法律责任。如若转载，请注明出处：http://www.rhkb.cn/news/73580.html

如若内容造成侵权/违法违规/事实不符，请联系长河编程网进行投诉反馈email:809451989@qq.com，一经查实，立即删除！

相关文章

两个镜头、视野、分辨率不同的相机（rgb、红外）的视野校正

两个镜头、视野、分辨率不同的相机（rgb、红外）的视野校正

文章目录 背景实际效果查找资料资料1资料2 解决方案最终结果 背景 目前在做的项目用到两个摄像头&#xff0c;一个是热成像摄像头、另一个是普通的rgb摄像头。 一开始的目标是让他们像素级重合&#xff0c;使得点击rgb图像时&#xff0c;即可知道其像素对应的温度。但是在尝试…
阅读更多...
js中的设计模式

js中的设计模式

设计模式 代码整体的结构会更加清楚&#xff0c;管理起来会更加方便&#xff0c;更好地维护 设计模式是一种思想 发布订阅 模块化开发 导入很多模块 容器即数组存储未来要执行的方法&#xff0c;同addEventListener 数组塌陷问题* 由于删除了元素&#xff0c;导致从删除元素的位…
阅读更多...
ppt怎么压缩到10m以内？分享好用的压缩方法

ppt怎么压缩到10m以内？分享好用的压缩方法

PPT是一种常见的演示文稿格式&#xff0c;有时候文件过大&#xff0c;我们会遇到无法发送、上传的现象&#xff0c;这时候简单的解决方法就是压缩其大小&#xff0c;那怎么才能将PPT压缩到10M以内呢&#xff1f; PPT文件大小受到影响的主要因素就是以下几点&#xff1a; 1、图…
阅读更多...
VR全景旅游，智慧文旅发展新趋势！

VR全景旅游，智慧文旅发展新趋势！

引言&#xff1a; VR全景旅游正在带领我们踏上一场全新的旅行体验。这种沉浸式的旅行方式&#xff0c;让我们可以足不出户&#xff0c;却又身临其境地感受世界各地的美景。 一&#xff0e;VR全景旅游是什么&#xff1f; VR全景旅游是一种借助虚拟现实技术&#xff0c;让用户…
阅读更多...
AssetBundle学习

AssetBundle学习

官方文档&#xff1a;AssetBundle 工作流程 - Unity 手册 (unity3d.com) 之前写的博客&#xff1a;AssetBundle学习_zaizai1007的博客-CSDN博客 使用流程图&#xff1a; 1&#xff0c;指定资源的AssetBundle属性 &#xff08;xxxa/xxx&#xff09;这里xxxa会生成目录&…
阅读更多...
Arcgis 分区统计majority参数统计问题

Arcgis 分区统计majority参数统计问题

利用Arcgis 进行分区统计时&#xff0c;需要统计不同矢量区域中栅格数据的众数&#xff08;majority&#xff09;&#xff0c;出现无法统计majority参数问题解决 解决&#xff1a;利用copy raster工具&#xff0c;将原始栅格数据 64bit转为16bit
阅读更多...
iOS 应用上架流程详解

iOS 应用上架流程详解

iOS 应用上架流程详解 欢迎来到我的博客&#xff0c;今天我将为大家分享 iOS 应用上架的详细流程。在这个数字化时代&#xff0c;移动应用已经成为了人们生活中不可或缺的一部分&#xff0c;而 iOS 平台的 App Store 则是开发者们发布应用的主要渠道之一。因此&#xff0c;了解…
阅读更多...
Vision Transformer （ViT）：图像分块、图像块嵌入、类别标记、QKV矩阵与自注意力机制的解析

Vision Transformer （ViT）：图像分块、图像块嵌入、类别标记、QKV矩阵与自注意力机制的解析

作者&#xff1a;CSDN _养乐多_ 本文将介绍Vision Transformers &#xff08;ViT&#xff09;中的关键点。包括图像分块&#xff08;Image Patching&#xff09;、图像块嵌入&#xff08;Patch Embedding&#xff09;、类别标记、&#xff08;class_token&#xff09;、QKV矩…
阅读更多...
微服务 云原生：搭建 K8S 集群

微服务 云原生：搭建 K8S 集群

为节约时间和成本&#xff0c;仅供学习使用&#xff0c;直接在两台虚拟机上模拟 K8S 集群搭建 踩坑之旅 系统环境&#xff1a;CentOS-7-x86_64-Minimal-2009 镜像&#xff0c;为方便起见&#xff0c;直接在 root 账户下操作&#xff0c;现实情况最好不要这样做。 基础准备 关…
阅读更多...
pycharm——涟漪散点图

pycharm——涟漪散点图

from pyecharts import options as opts from pyecharts.charts import EffectScatterc (EffectScatter().add_xaxis( ["高等数学1&#xff0c;2","C语言程序设计","python程序设计","大数据导论","数据结构","大数据…
阅读更多...
CentOS 8 上安装 Nginx

CentOS 8 上安装 Nginx

Nginx是一款高性能的开源Web服务器和反向代理服务器&#xff0c;以其轻量级和高效能而广受欢迎。在本教程中&#xff0c;我们将学习在 CentOS 8 操作系统上安装和配置 Nginx。 步骤 1&#xff1a;更新系统 在安装任何软件之前&#xff0c;让我们先更新系统的软件包列表和已安…
阅读更多...
opencv 31-图像平滑处理-方框滤波cv2.boxFilter()

opencv 31-图像平滑处理-方框滤波cv2.boxFilter()

方框滤波&#xff08;Box Filtering&#xff09;是一种简单的图像平滑处理方法&#xff0c;它主要用于去除图像中的噪声和减少细节&#xff0c;同时保持图像的整体亮度分布。 方框滤波的原理很简单&#xff1a;对于图像中的每个像素&#xff0c;将其周围的一个固定大小的邻域内…
阅读更多...
HTTP、HTTPS协议详解

HTTP、HTTPS协议详解

文章目录 HTTP是什么报文结构请求头部响应头部 工作原理用户点击一个URL链接后&#xff0c;浏览器和web服务器会执行什么http的版本持久连接和非持久连接无状态与有状态Cookie和Sessionhttp方法&#xff1a;get和post的区别 状态码 HTTPS是什么ssl如何搞到证书nginx中的部署 加…
阅读更多...
Sqli-labs1~65关 通关详解 解题思路+解题步骤+解析

Sqli-labs1~65关 通关详解 解题思路+解题步骤+解析

Sqli-labs 01关 (web517) 输入?id1 正常 输入?id1 报错 .0 输入?id1-- 正常判断是字符型注入&#xff0c;闭合方式是这里插一句。limit 100,1是从第100条数据开始&#xff0c;读取1条数据。limit 6是读取前6条数据。 ?id1 order by 3-- 正常判断回显位有三个。?id…
阅读更多...
ChatGPT在法律行业的市场潜力

ChatGPT在法律行业的市场潜力

​ChatGPT现在已经成为我们的文字生成辅助工具、搜索引擎助手&#xff0c;许多体验过它的朋友会发现对它越来越依赖&#xff0c;并将其逐渐融入到自己的日常工作、生活。但有一点值得注意&#xff1a;这种人工智能除了技术可行、经济价值可行还要与相关规范即人类普遍的价值观念…
阅读更多...
轻松批量文件改名！一键翻译重命名文件夹/文件，省时高效！」

轻松批量文件改名！一键翻译重命名文件夹/文件，省时高效！」

繁忙的数字时代&#xff0c;我们经常需要处理大量的文件和文件夹。而手动逐个更改文件名不仅费时费力&#xff0c;还容易出错。因此&#xff0c;我们为您带来了一款强大的工具——批量文件改名软件&#xff01;现在&#xff0c;您可以一键翻译重命名文件夹和文件&#xff0c;轻…
阅读更多...
csdn新星计划vue3+ts+antd赛道——利用inscode搭建vue3(ts)+antd前端模板

csdn新星计划vue3+ts+antd赛道——利用inscode搭建vue3(ts)+antd前端模板

文章目录 ⭐前言⭐利用inscode免费开放资源&#x1f496; 在inscode搭建vue3tsant项目&#x1f496; 调整配置&#x1f496; antd 国际化配置&#x1f496; 用户store&#x1f496; 路由权限&#x1f496; 预览 ⭐结束 ⭐前言 大家好&#xff0c;我是yma16&#xff0c;本文分享…
阅读更多...
Day10-作业（SpringBootWeb案例）

Day10-作业（SpringBootWeb案例）

作业1&#xff1a;完成课上预留给大家自己完成的功能 【部门管理的修改功能】 注意&#xff1a; 部门管理的修改功能&#xff0c;需要开发两个接口&#xff1a; 先开发根据ID查询部门信息的接口&#xff0c;该接口用户查询数据并展示 。(一定一定先做这个功能) 再开发根据ID…
阅读更多...
YOLOv5改进系列（18）——更换Neck之AFPN（全新渐进特征金字塔|超越PAFPN|实测涨点）

YOLOv5改进系列（18）——更换Neck之AFPN（全新渐进特征金字塔|超越PAFPN|实测涨点）

【YOLOv5改进系列】前期回顾： YOLOv5改进系列（0）——重要性能指标与训练结果评价及分析 YOLOv5改进系列（1）——添加SE注意力机制
阅读更多...
[JAVA基础]自动拆装箱NPE问题

[JAVA基础]自动拆装箱NPE问题

1.自动拆装箱场景 自动装箱 当把字面量转换成包装类的时候会自动装箱 比如&#xff1a; Integer a 1; Integer b 1; 自动拆箱 当你对包装类的对象进行运算&#xff08;如加法、减法等&#xff09;时&#xff0c;Java会自动进行拆箱操作。拆箱是将包装类型的对象转换为相应的基…
阅读更多...
最新文章
推荐文章

Copyright @ 2022~2023

友情链接： 我的编程经验分享 一条长河网 尧图网站开发