Quantum supremacy using a programmable superconducting processor 全文翻译，配公式和图

2019年，谷歌的量子霸权文章，

原文链接：

https://www.nature.com/articles/s41586-019-1666-5

第一稿，公式和视图后续再加。。。

Quantum supremacy using a programmable superconducting processor
使用可编程超导处理器的量子霸权

Abstract

The promise of quantum computers is that certain computational tasks might be executed exponentially faster on a quantum processor than on a classical processor1. A fundamental challenge is to build a high-fidelity processor capable of running quantum algorithms in an exponentially large computational space. Here we report the use of a processor with programmable superconducting qubits to create quantum states on 53 qubits, corresponding to a computational state-space of dimension 2^53 (about 10^16). Measurements from repeated experiments sample the resulting probability distribution, which we verify using classical simulations. Our Sycamore processor takes about 200 seconds to sample one instance of a quantum circuit a million times—our benchmarks currently indicate that the equivalent task for a state-of-the-art classical supercomputer would take approximately 10,000 years. This dramatic increase in speed compared to all known classical algorithms is an experimental realization of quantum supremacy for this specific computational task, heralding a much-anticipated computing paradigm.

摘要

量子计算机的前景在于某些计算任务在量子处理器上执行的速度可能比在经典处理器上快指数级别。一个基本的挑战是构建一个高保真度的处理器，能够在指数级大的计算空间中运行量子算法。在这里，我们报告了使用可编程超导量子比特的处理器在53个量子比特上创建量子态，对应于维度为2^53（约为10^16）的计算状态空间。通过重复实验的测量，我们对结果概率分布进行了采样，并使用经典模拟进行了验证。我们的 Sycamore 处理器大约需要200秒来对一个量子电路的一个实例进行一百万次采样——我们的基准测试目前表明，最先进的经典超级计算机完成相同任务大约需要10,000年。与所有已知经典算法相比，这种速度的显著提升是对这一特定计算任务的量子优势的实验实现，预示着一个备受期待的计算范式的到来。

main

In the early 1980s, Richard Feynman proposed that a quantum computer would be an effective tool with which to solve problems in physics and chemistry, given that it is exponentially costly to simulate large quantum systems with classical computers. Realizing Feynman’s vision poses substantial experimental and theoretical challenges. First, can a quantum system be engineered to perform a computation in a large enough computational (Hilbert) space and with a low enough error rate to provide a quantum speedup? Second, can we formulate a problem that is hard for a classical computer but easy for a quantum computer? By computing such a benchmark task on our superconducting qubit processor, we tackle both questions. Our experiment achieves quantum supremacy, a milestone on the path to full-scale quantum computing.
/suːˈpreməsi/

主要内容

在1980年代初，理查德·费曼提出，量子计算机将是解决物理和化学问题的有效工具，因为用经典计算机模拟大型量子系统的成本是指数级的。实现费曼的愿景面临着重大的实验和理论挑战。首先，能否设计一个量子系统，使其在足够大的计算（希尔伯特）空间中执行计算，并且具有足够低的错误率以提供量子加速？其次，能否提出一个对经典计算机来说困难但对量子计算机来说容易的问题？通过在我们的超导量子比特处理器上计算这样的基准任务，我们解决了这两个问题。我们的实验实现了量子优势，这是通往全规模量子计算的一个里程碑。

In reaching this milestone, we show that quantum speedup is achievable in a real-world system and is not precluded by any hidden physical laws. Quantum supremacy also heralds the era of noisy intermediate-scale quantum (NISQ) technologies. The benchmark task we demonstrate has an immediate application in generating certifiable random numbers (S. Aaronson, manuscript in preparation); other initial uses for this new computational capability may include optimization, machine learning, materials science and chemistry. However, realizing the full promise of quantum computing (using Shor’s algorithm for factoring, for example) still requires technical leaps to engineer fault-tolerant logical qubits.

在达到这一里程碑时，我们展示了量子加速在现实世界系统中是可实现的，并且不受任何隐藏物理法则的限制。量子优势也预示着带噪声中间规模量子（NISQ）技术的时代。我们展示的基准任务在生成可认证的随机数方面具有直接应用（S. Aaronson，手稿在准备中）；这种新计算能力的其他初步用途可能包括优化、机器学习、材料科学和化学。然而，实现量子计算的全部潜力（例如使用 Shor 算法进行因式分解）仍然需要技术上的飞跃，以建造有容错能力的逻辑量子比特。

To achieve quantum supremacy, we made a number of technical advances which also pave the way towards error correction. We developed fast, high-fidelity gates that can be executed simultaneously across a two-dimensional qubit array. We calibrated and benchmarked the processor at both the component and system level using a powerful new tool: cross-entropy benchmarking. Finally, we used component-level fidelities to accurately predict the performance of the whole system, further showing that quantum information behaves as expected when scaling to large systems.

为了实现量子优势，我们进行了多项技术进步，这些进步也为错误纠正铺平了道路。我们开发了快速、高保真度的门，可以在二维量子比特阵列上同时执行。我们使用一种强大的新工具：交叉熵基准测试，对处理器在组件和系统级别进行了校准和基准测试。最后，我们使用组件级别的保真度准确预测了整个系统的性能，进一步表明量子信息在扩展到大系统时表现如预期。

A suitable computational task

To demonstrate quantum supremacy, we compare our quantum processor against state-of-the-art classical computers in the task of sampling the output of a pseudo-random quantum circuit. Random circuits are a suitable choice for benchmarking because they do not possess structure and therefore allow for limited guarantees of computational hardness. We design the circuits to entangle a set of quantum bits (qubits) by repeated application of single-qubit and two-qubit logical operations. Sampling the quantum circuit’s output produces a set of bitstrings, for example {0000101, 1011100, …}. Owing to quantum interference, the probability distribution of the bitstrings resembles a speckled intensity pattern produced by light interference in laser scatter, such that some bitstrings are much more likely to occur than others. Classically computing this probability distribution becomes exponentially more difficult as the number of qubits (width) and number of gate cycles (depth) grow.

一个合适的计算任务

为了展示量子优势，我们将我们的量子处理器与最先进的经典计算机进行比较，任务是对伪随机量子电路的输出进行采样。随机电路是基准测试的合适选择，因为它们没有结构，因此对计算难度的保证有限。我们设计电路，通过重复应用单量子比特和双量子比特的逻辑操作来纠缠一组量子比特（qubits）。对量子电路输出的采样产生一组比特串，例如 {0000101, 1011100, …}。由于量子干涉，比特串的概率分布类似于激光散射中光干涉产生的斑点强度图案，因此某些比特串的出现概率远高于其他比特串。随着量子比特数量（宽度）和门周期数量（深度）的增加，经典计算这个概率分布变得指数级困难。

We verify that the quantum processor is working properly using a method called cross-entropy benchmarking, which compares how often each bitstring is observed experimentally with its corresponding ideal probability computed via simulation on a classical computer. For a given circuit, we collect the measured bitstrings {xi} and compute the linear cross-entropy benchmarking fidelity (see also Supplementary Information), which is the mean of the simulated probabilities of the bitstrings we measured:

我们使用一种称为交叉熵基准测试的方法来验证量子处理器的正常工作，该方法比较每个比特串在实验中观察到的频率与通过经典计算机模拟计算的相应理想概率。对于给定的电路，我们收集测量到的比特串 {xi} 并计算线性交叉熵基准测试保真度（另见补充信息），即我们测量的比特串的模拟概率的平均值：

where n is the number of qubits, P(xi) is the probability of bitstring xi computed for the ideal quantum circuit, and the average is over the observed bitstrings. Intuitively, is correlated with how often we sample high-probability bitstrings. When there are no errors in the quantum circuit, the distribution of probabilities is exponential (see Supplementary Information), and sampling from this distribution will produce . On the other hand, sampling from the uniform distribution will give ⟨P(xi)⟩i = 1/2n and produce . Values of between 0 and 1 correspond to the probability that no error has occurred while running the circuit. The probabilities P(xi) must be obtained from classically simulating the quantum circuit, and thus computing is intractable in the regime of quantum supremacy. However, with certain circuit simplifications, we can obtain quantitative fidelity estimates of a fully operating processor running wide and deep quantum circuits.

其中 n 是量子比特的数量，P(xi) 是为理想量子电路计算的比特串 xi 的概率，平均值是针对观察到的比特串。直观上，F 与我们采样高概率比特串的频率相关。当量子电路没有错误时，概率分布是指数级的（见补充信息），从这个分布中采样将产生高概率比特串。另一方面，从均匀分布中采样将给出 ⟨P(xi)⟩i = 1/2^n，并产生低概率比特串。F 的值在 0 和 1 之间对应于在运行电路时没有发生错误的概率。概率 P(xi) 必须通过经典模拟量子电路获得，因此在量子优势的范围内计算 F 是不可行的。然而，通过某些电路简化，我们可以获得运行宽且深的量子电路的完全操作处理器的定量保真度估计。

Our goal is to achieve a high enough for a circuit with sufficient width and depth such that the classical computing cost is prohibitively large. This is a difficult task because our logic gates are imperfect and the quantum states we intend to create are sensitive to errors. A single bit or phase flip over the course of the algorithm will completely shuffle the speckle pattern and result in close to zero fidelity (see also Supplementary Information). Therefore, in order to claim quantum supremacy we need a quantum processor that executes the program with sufficiently low error rates.

我们的目标是为具有足够宽度和深度的电路实现足够高的 F，使得经典计算成本变得不可承受。这是一项困难的任务，因为我们的逻辑门并不完美，而我们打算创建的量子态对错误非常敏感。在算法执行过程中，单个比特或相位翻转将完全打乱斑点图案，并导致接近零的保真度（另见补充信息）。因此，为了声称量子优势，我们需要一个以足够低的错误率执行程序的量子处理器。

Building a high-fidelity processor

We designed a quantum processor named ‘Sycamore’ which consists of a two-dimensional array of 54 transmon qubits, where each qubit is tunably coupled to four nearest neighbours, in a rectangular lattice. The connectivity was chosen to be forward-compatible with error correction using the surface code. A key systems engineering advance of this device is achieving high-fidelity single- and two-qubit operations, not just in isolation but also while performing a realistic computation with simultaneous gate operations on many qubits. We discuss the highlights below; see also the Supplementary Information.

构建高保真度处理器

我们设计了一种名为“Sycamore”的量子处理器，它由一个包含54个超导量子比特的二维阵列组成，其中每个量子比特可调地与四个最近邻耦合，形成一个矩形晶格。连接性选择为与使用表面码的错误纠正向前兼容。该设备的一个关键系统工程进展是实现高保真度的单量子比特和双量子比特操作，不仅在孤立状态下，而且在对多个量子比特进行同时门操作的实际计算中。我们在下面讨论了亮点；另见补充信息。

In a superconducting circuit, conduction electrons condense into a macroscopic quantum state, such that currents and voltages behave quantum mechanically. Our processor uses transmon qubits, which can be thought of as nonlinear superconducting resonators at 5–7 GHz. The qubit is encoded as the two lowest quantum eigenstates of the resonant circuit. Each transmon has two controls: a microwave drive to excite the qubit, and a magnetic flux control to tune the frequency. Each qubit is connected to a linear resonator used to read out the qubit state. As shown in Fig. 1, each qubit is also connected to its neighbouring qubits using a new adjustable coupler. Our coupler design allows us to quickly tune the qubit–qubit coupling from completely off to 40 MHz. One qubit did not function properly, so the device uses 53 qubits and 86 couplers.

在超导电路中，导电电子凝聚成宏观量子态，使得电流和电压表现出量子力学特性。我们的处理器使用超导量子比特，可以视为在5–7 GHz下的非线性超导谐振器。量子比特被编码为谐振电路的两个最低量子本征态。每个超导量子比特有两个控制：一个微波驱动用于激发量子比特，另一个磁通控制用于调谐频率。每个量子比特连接到一个线性谐振器，用于读取量子比特状态。如图1所示，每个量子比特还通过一种新的可调耦合器与其邻近的量子比特连接。我们的耦合器设计使我们能够快速调节量子比特之间的耦合，从完全关闭到40 MHz。由于一个量子比特未能正常工作，因此该设备使用53个量子比特和86个耦合器。

The processor is fabricated using aluminium for metallization and Josephson junctions, and indium for bump-bonds between two silicon wafers. The chip is wire-bonded to a superconducting circuit board and cooled to below 20 mK in a dilution refrigerator to reduce ambient thermal energy to well below the qubit energy. The processor is connected through filters and attenuators to room-temperature electronics, which synthesize the control signals. The state of all qubits can be read simultaneously by using a frequency-multiplexing technique. We use two stages of cryogenic amplifiers to boost the signal, which is digitized (8 bits at 1 GHz) and demultiplexed digitally at room temperature. In total, we orchestrate 277 digital-to-analog converters (14 bits at 1 GHz) for complete control of the quantum processor.

该处理器使用铝作为金属化和约瑟夫森结的材料，使用铟作为两个硅晶圆之间的凸点连接。芯片通过线焊接到超导电路板上，并在稀释制冷机中冷却至低于20 mK，以将环境热能降低到远低于量子比特的能量。处理器通过滤波器和衰减器连接到室温电子设备，这些设备合成控制信号。所有量子比特的状态可以通过频率复用技术同时读取。我们使用两个阶段的低温放大器来增强信号，该信号被数字化（8位，1 GHz）并在室温下进行数字解复用。总的来说，我们协调了277个数模转换器（14位，1 GHz），以实现对量子处理器的完全控制。

We execute single-qubit gates by driving 25-ns microwave pulses resonant with the qubit frequency while the qubit–qubit coupling is turned off. The pulses are shaped to minimize transitions to higher transmon states. Gate performance varies strongly with frequency owing to two-level-system defects, stray microwave modes, coupling to control lines and the readout resonator, residual stray coupling between qubits, flux noise and pulse distortions. We therefore optimize the single-qubit operation frequencies to mitigate these error mechanisms.

我们通过驱动与量子比特频率共振的25纳秒微波脉冲来执行单量子比特门，同时关闭量子比特之间的耦合。脉冲的形状经过调整，以最小化向更高的超导量子比特状态的跃迁。由于二级系统缺陷、杂散微波模式、与控制线和读取谐振器的耦合、量子比特之间的残余杂散耦合、磁通噪声和脉冲失真，门的性能在频率上变化很大。因此，我们优化单量子比特操作的频率，以减轻这些错误机制。

We benchmark single-qubit gate performance by using the cross-entropy benchmarking protocol described above, reduced to the single-qubit level (n = 1), to measure the probability of an error occurring during a single-qubit gate. On each qubit, we apply a variable number m of randomly selected gates and measure averaged over many sequences; as m increases, errors accumulate and average decays. We model this decay by [1 − e1/(1 − 1/D2)]m where e1 is the Pauli error probability. The state (Hilbert) space dimension term, D = 2n, which equals 2 for this case, corrects for the depolarizing model where states with errors partially overlap with the ideal state. This procedure is similar to the more typical technique of randomized benchmarking, but supports non-Clifford-gate sets and can separate out decoherence error from coherent control error. We then repeat the experiment with all qubits executing single-qubit gates simultaneously (Fig. 2), which shows only a small increase in the error probabilities, demonstrating that our device has low microwave crosstalk.

我们通过使用上述的交叉熵基准测试协议来基准测试单量子比特门的性能，该协议被简化到单量子比特级别（n = 1），以测量在单量子比特门操作期间发生错误的概率。在每个量子比特上，我们应用一个可变数量 m 的随机选择的门，并测量平均值；随着 m 的增加，错误累积，平均值衰减。我们通过以下模型来描述这种衰减：[1 − e1/(1 − 1/D2)]^m，其中 e1 是泡利错误概率。状态（希尔伯特）空间维度项 D = 2^n，在这种情况下等于2，修正了去极化模型，其中带有错误的状态与理想状态部分重叠。该过程类似于更典型的随机基准测试技术，但支持非克利福德门集，并可以将去相干错误与相干控制错误分离。然后，我们重复实验，让所有量子比特同时执行单量子比特门（图2），这表明错误概率仅小幅增加，证明我们的设备具有低微波串扰。

We perform two-qubit iSWAP-like entangling gates by bringing neighbouring qubits on-resonance and turning on a 20-MHz coupling for 12 ns, which allows the qubits to swap excitations. During this time, the qubits also experience a controlled-phase (CZ) interaction, which originates from the higher levels of the transmon. The two-qubit gate frequency trajectories of each pair of qubits are optimized to mitigate the same error mechanisms considered in optimizing single-qubit operation frequencies.
我们通过使相邻量子比特共振并开启20 MHz的耦合12纳秒来执行类似iSWAP的双量子比特纠缠门，这允许量子比特交换激发。在此期间，量子比特还经历了来自超导量子比特高能级的受控相位（CZ）相互作用。每对量子比特的双量子比特门频率轨迹经过优化，以减轻在优化单量子比特操作频率时考虑的相同错误机制。

To characterize and benchmark the two-qubit gates, we run two-qubit circuits with m cycles, where each cycle contains a randomly chosen single-qubit gate on each of the two qubits followed by a fixed two-qubit gate. We learn the parameters of the two-qubit unitary (such as the amount of iSWAP and CZ interaction) by using as a cost function. After this optimization, we extract the per-cycle error e2c from the decay of with m, and isolate the two-qubit error e2 by subtracting the two single-qubit errors e1. We find an average e2 of 0.36%. Additionally, we repeat the same procedure while simultaneously running two-qubit circuits for the entire array. After updating the unitary parameters to account for effects such as dispersive shifts and crosstalk, we find an average e2 of 0.62%.

为了表征和基准测试双量子比特门，我们运行具有m个周期的双量子比特电路，其中每个周期包含对两个量子比特上随机选择的单量子比特门，后跟一个固定的双量子比特门。我们通过使用作为成本函数来学习双量子比特单位的参数（例如iSWAP和CZ相互作用的量）。在此优化之后，我们从与m的衰减中提取每周期错误 e2c，并通过减去两个单量子比特错误 e1 来隔离双量子比特错误 e2。我们发现平均 e2 为0.36%。此外，我们在整个阵列同时运行双量子比特电路时重复相同的过程。在更新单位参数以考虑色散偏移和串扰等效应后，我们发现平均 e2 为0.62%。

For the full experiment, we generate quantum circuits using the two-qubit unitaries measured for each pair during simultaneous operation, rather than a standard gate for all pairs. The typical two-qubit gate is a full iSWAP with 1/6th of a full CZ. Using individually calibrated gates in no way limits the universality of the demonstration. One can compose, for example, controlled-NOT (CNOT) gates from 1-qubit gates and two of the unique 2-qubit gates of any given pair. The implementation of high-fidelity ‘textbook gates’ natively, such as CZ or , is work in progress.

对于完整实验，我们使用在同时操作期间为每对量子比特测量的双量子比特单位生成量子电路，而不是为所有对使用标准门。典型的双量子比特门是完整的iSWAP，带有1/6的完整CZ。使用单独校准的门并不会限制演示的通用性。例如，可以从单量子比特门和任何给定对的两个独特双量子比特门组合出受控非门（CNOT）。高保真度“教科书门”的本地实现，例如CZ或其他门，仍在进行中。

Finally, we benchmark qubit readout using standard dispersive measurement. Measurement errors averaged over the 0 and 1 states are shown in Fig. 2a. We have also measured the error when operating all qubits simultaneously, by randomly preparing each qubit in the 0 or 1 state and then measuring all qubits for the probability of the correct result. We find that simultaneous readout incurs only a modest increase in per-qubit measurement errors.

最后，我们使用标准的色散测量对量子比特读取进行基准测试。图2a显示了在0和1状态下的测量错误的平均值。我们还测量了同时操作所有量子比特时的错误，通过随机准备每个量子比特为0或1状态，然后测量所有量子比特以获取正确结果的概率。我们发现，同时读取仅导致每个量子比特测量错误的适度增加。

Having found the error rates of the individual gates and readout, we can model the fidelity of a quantum circuit as the product of the probabilities of error-free operation of all gates and measurements. Our largest random quantum circuits have 53 qubits, 1,113 single-qubit gates, 430 two-qubit gates, and a measurement on each qubit, for which we predict a total fidelity of 0.2%. This fidelity should be resolvable with a few million measurements, since the uncertainty on is , where Ns is the number of samples. Our model assumes that entangling larger and larger systems does not introduce additional error sources beyond the errors we measure at the single- and two-qubit level. In the next section we will see how well this hypothesis holds up.

在找到单个门和读取的错误率后，我们可以将量子电路的保真度建模为所有门和测量的无错误操作概率的乘积。我们最大的随机量子电路有53个量子比特、1,113个单量子比特门、430个双量子比特门，以及对每个量子比特的测量，我们预测总保真度为0.2%。这个保真度应该可以通过几百万次测量来解决，因为对保真度的误差为1/√Ns，其中 Ns 是样本数量。我们的模型假设，纠缠越来越大的系统不会引入超出我们在单量子比特和双量子比特水平上测量的错误源。在下一部分中，我们将看到这一假设的有效性。

Fidelity estimation in the supremacy regime

The gate sequence for our pseudo-random quantum circuit generation is shown in Fig. 3. One cycle of the algorithm consists of applying single-qubit gates chosen randomly from on all qubits, followed by two-qubit gates on pairs of qubits. The sequences of gates which form the ‘supremacy circuits’ are designed to minimize the circuit depth required to create a highly entangled state, which is needed for computational complexity and classical hardness.

在优势领域的保真度估计

我们伪随机量子电路生成的门序列如图3所示。算法的一个周期包括在所有量子比特上应用从中随机选择的单量子比特门，随后在量子比特对上应用双量子比特门。形成“优势电路”的门序列旨在最小化创建高度纠缠态所需的电路深度，这对于计算复杂性和经典难度是必要的。

Although we cannot compute in the supremacy regime, we can estimate it using three variations to reduce the complexity of the circuits. In ‘patch circuits’, we remove a slice of two-qubit gates (a small fraction of the total number of two-qubit gates), splitting the circuit into two spatially isolated, non-interacting patches of qubits. We then compute the total fidelity as the product of the patch fidelities, each of which can be easily calculated. In ‘elided circuits’, we remove only a fraction of the initial two-qubit gates along the slice, allowing for entanglement between patches, which more closely mimics the full experiment while still maintaining simulation feasibility. Finally, we can also run full ‘verification circuits’, with the same gate counts as our supremacy circuits, but with a different pattern for the sequence of two-qubit gates, which is much easier to simulate classically (see also Supplementary Information). Comparison between these three variations allows us to track the system fidelity as we approach the supremacy regime.

尽管我们无法在优势领域计算保真度，但我们可以使用三种变体来估计它，以降低电路的复杂性。在“补丁电路”中，我们移除一片双量子比特门（占总双量子比特门数量的一小部分），将电路分割成两个空间上隔离、非相互作用的量子比特补丁。然后，我们将总保真度计算为补丁保真度的乘积，每个补丁保真度都可以轻松计算。在“省略电路”中，我们仅沿切片移除一部分初始双量子比特门，允许补丁之间的纠缠，这更接近完整实验，同时仍保持模拟的可行性。最后，我们还可以运行完整的“验证电路”，其门数与我们的优势电路相同，但双量子比特门的序列模式不同，这在经典上更容易模拟（另见补充信息）。这三种变体之间的比较使我们能够跟踪系统保真度，随着我们接近优势领域。

We first check that the patch and elided versions of the verification circuits produce the same fidelity as the full verification circuits up to 53 qubits, as shown in Fig. 4a. For each data point, we typically collect Ns = 5 × 106 total samples over ten circuit instances, where instances differ only in the choices of single-qubit gates in each cycle. We also show predicted values, computed by multiplying the no-error probabilities of single- and two-qubit gates and measurement (see also Supplementary Information). The predicted, patch and elided fidelities all show good agreement with the fidelities of the corresponding full circuits, despite the vast differences in computational complexity and entanglement. This gives us confidence that elided circuits can be used to accurately estimate the fidelity of more-complex circuits.

我们首先检查补丁和省略版本的验证电路在53个量子比特下产生的保真度是否与完整验证电路相同，如图4a所示。对于每个数据点，我们通常在十个电路实例上收集Ns = 5 × 10^6个总样本，其中实例仅在每个周期的单量子比特门选择上有所不同。我们还展示了预测的保真度值，通过将单量子比特门和双量子比特门及测量的无错误概率相乘计算得出（另见补充信息）。预测的、补丁的和省略的保真度与相应完整电路的保真度都显示出良好的一致性，尽管计算复杂性和纠缠程度差异巨大。这使我们有信心，省略电路可以用来准确估计更复杂电路的保真度。

The largest circuits for which the fidelity can still be directly verified have 53 qubits and a simplified gate arrangement. Performing random circuit sampling on these at 0.8% fidelity takes one million cores 130 seconds, corresponding to a million-fold speedup of the quantum processor relative to a single core.

可以直接验证的最大电路具有53个量子比特和简化的门排列。在这些电路上以0.8%的保真度进行随机电路采样需要一百万个核心130秒，相当于量子处理器相对于单个核心的百万倍加速。

We proceed now to benchmark our computationally most difficult circuits, which are simply a rearrangement of the two-qubit gates. In Fig. 4b, we show the measured for 53-qubit patch and elided versions of the full supremacy circuits with increasing depth. For the largest circuit with 53 qubits and 20 cycles, we collected Ns = 30 × 106 samples over ten circuit instances, obtaining for the elided circuits. With 5σ confidence, we assert that the average fidelity of running these circuits on the quantum processor is greater than at least 0.1%. We expect that the full data for Fig. 4b should have similar fidelities, but since the simulation times (red numbers) take too long to check, we have archived the data (see ‘Data availability’ section). The data is thus in the quantum supremacy regime.

我们现在继续基准测试我们计算上最困难的电路，这些电路只是双量子比特门的重新排列。在图4b中，我们展示了53个量子比特的补丁和省略版本的完整优势电路的测量保真度，随着深度的增加。对于具有53个量子比特和20个周期的最大电路，我们在十个电路实例上收集了Ns = 30 × 10^6个样本，获得了省略电路的保真度。以5σ的置信度，我们断言在量子处理器上运行这些电路的平均保真度大于至少0.1%。我们预计图4b的完整数据应具有类似的保真度，但由于模拟时间（红色数字）过长而无法检查，因此我们已归档数据（见“数据可用性”部分）。因此，这些数据处于量子优势领域。

The classical computational cost

We simulate the quantum circuits used in the experiment on classical computers for two purposes: (1) verifying our quantum processor and benchmarking methods by computing where possible using simplifiable circuits (Fig. 4a), and (2) estimating as well as the classical cost of sampling our hardest circuits (Fig. 4b). Up to 43 qubits, we use a Schrödinger algorithm, which simulates the evolution of the full quantum state; the Jülich supercomputer (with 100,000 cores, 250 terabytes) runs the largest cases. Above this size, there is not enough random access memory (RAM) to store the quantum state. For larger qubit numbers, we use a hybrid Schrödinger–Feynman algorithm running on Google data centres to compute the amplitudes of individual bitstrings. This algorithm breaks the circuit up into two patches of qubits and efficiently simulates each patch using a Schrödinger method, before connecting them using an approach reminiscent of the Feynman path-integral. Although it is more memory-efficient, the Schrödinger–Feynman algorithm becomes exponentially more computationally expensive with increasing circuit depth owing to the exponential growth of paths with the number of gates connecting the patches.

经典计算成本

我们在经典计算机上模拟实验中使用的量子电路，出于两个目的：（1）通过使用可简化电路计算保真度来验证我们的量子处理器和基准测试方法（图4a），以及（2）估计保真度以及采样我们最困难电路的经典成本（图4b）。对于最多43个量子比特，我们使用薛定谔算法，该算法模拟完整量子态的演化；于利希超级计算机（具有100,000个核心，250TB内存）运行最大案例。超过此规模，随机存取内存（RAM）不足以存储量子态。对于更大的量子比特数，我们使用在谷歌数据中心运行的混合薛定谔-费曼算法来计算单个比特串的幅度。该算法将电路分成两个量子比特补丁，并使用薛定谔方法高效模拟每个补丁，然后使用类似于费曼路径积分的方法将它们连接起来。尽管它在内存使用上更高效，但由于连接补丁的门数量的指数增长，薛定谔-费曼算法在电路深度增加时变得计算上指数级昂贵。

To estimate the classical computational cost of the supremacy circuits (grey numbers in Fig. 4b), we ran portions of the quantum circuit simulation on both the Summit supercomputer as well as on Google clusters and extrapolated to the full cost. In this extrapolation, we account for the computation cost of sampling by scaling the verification cost with , for example, a 0.1% fidelity decreases the cost by about 1,000. On the Summit supercomputer, which is currently the most powerful in the world, we used a method inspired by Feynman path-integrals that is most efficient at low depth. At m = 20 the tensors do not reasonably fit into node memory, so we can only measure runtimes up to m = 14, for which we estimate that sampling three million bitstrings with 1% fidelity would require a year.

为了估计优势电路的经典计算成本（图4b中的灰色数字），我们在Summit超级计算机和谷歌集群上运行了量子电路模拟的部分，并推断出完整成本。在此推断中，我们通过将验证成本按保真度进行缩放来考虑采样的计算成本，例如，0.1%的保真度将成本降低约1,000倍。在目前世界上最强大的Summit超级计算机上，我们使用了一种受费曼路径积分启发的方法，该方法在低深度时最有效。在m = 20时，张量无法合理地适应节点内存，因此我们只能测量到m = 14的运行时间，对于此情况，我们估计以1%保真度采样三百万个比特串将需要一年。

On Google Cloud servers, we estimate that performing the same task for m = 20 with 0.1% fidelity using the Schrödinger–Feynman algorithm would cost 50 trillion core-hours and consume one petawatt hour of energy. To put this in perspective, it took 600 seconds to sample the circuit on the quantum processor three million times, where sampling time is limited by control hardware communications; in fact, the net quantum processor time is only about 30 seconds. The bitstring samples from all circuits have been archived online (see ‘Data availability’ section) to encourage development and testing of more advanced verification algorithms.

在谷歌云服务器上，我们估计使用薛定谔-费曼算法以0.1%保真度执行相同任务的成本为50万亿核心小时，并消耗一拍瓦时的能量。为了说明这一点，在量子处理器上对电路进行三百万次采样只需600秒，其中采样时间受控硬件通信的限制；实际上，净量子处理器时间仅约为30秒。所有电路的比特串样本已在线归档（见“数据可用性”部分），以鼓励开发和测试更先进的验证算法。

One may wonder to what extent algorithmic innovation can enhance classical simulations. Our assumption, based on insights from complexity theory, is that the cost of this algorithmic task is exponential in circuit size. Indeed, simulation methods have improved steadily over the past few years. We expect that lower simulation costs than reported here will eventually be achieved, but we also expect that they will be consistently outpaced by hardware improvements on larger quantum processors.

人们可能会想，算法创新在多大程度上可以增强经典模拟。我们基于复杂性理论的见解假设，这一算法任务的成本在电路规模上是指数级的。确实，模拟方法在过去几年中稳步改善。我们预计最终将实现比这里报告的更低的模拟成本，但我们也预计这些成本将始终被更大量子处理器的硬件改进所超越。

Verifying the digital error model

A key assumption underlying the theory of quantum error correction is that quantum state errors may be considered digitized and localized. Under such a digital model, all errors in the evolving quantum state may be characterized by a set of localized Pauli errors (bit-flips or phase-flips) interspersed into the circuit. Since continuous amplitudes are fundamental to quantum mechanics, it needs to be tested whether errors in a quantum system could be treated as discrete and probabilistic. Indeed, our experimental observations support the validity of this model for our processor. Our system fidelity is well predicted by a simple model in which the individually characterized fidelities of each gate are multiplied together (Fig. 4).

验证数字错误模型

量子错误纠正理论的一个关键假设是，量子态错误可以被视为数字化和局部化的。在这样的数字模型下，演变中的量子态中的所有错误可以通过一组局部的泡利错误（比特翻转或相位翻转）来表征，这些错误交错在电路中。由于连续幅度是量子力学的基础，因此需要测试量子系统中的错误是否可以被视为离散和概率性的。实际上，我们的实验观察支持了这一模型在我们处理器上的有效性。我们的系统保真度很好地被一个简单模型预测，该模型将每个门的单独特征保真度相乘（图4）。

To be successfully described by a digitized error model, a system should be low in correlated errors. We achieve this in our experiment by choosing circuits that randomize and decorrelate errors, by optimizing control to minimize systematic errors and leakage, and by designing gates that operate much faster than correlated noise sources, such as 1/f flux noise. Demonstrating a predictive uncorrelated error model up to a Hilbert space of size 253 shows that we can build a system where quantum resources, such as entanglement, are not prohibitively fragile.

为了成功地被数字化错误模型描述，系统应该具有较低的相关错误。在我们的实验中，我们通过选择随机化和去相关错误的电路、优化控制以最小化系统性错误和泄漏，以及设计比相关噪声源（如1/f磁通噪声）运行得更快的门来实现这一点。展示高达253维希尔伯特空间的无关错误模型的预测表明，我们可以构建一个量子资源（如纠缠）不至于过于脆弱的系统。

The future

Quantum processors based on superconducting qubits can now perform computations in a Hilbert space of dimension 253 ≈ 9 × 1015, beyond the reach of the fastest classical supercomputers available today. To our knowledge, this experiment marks the first computation that can be performed only on a quantum processor. Quantum processors have thus reached the regime of quantum supremacy. We expect that their computational power will continue to grow at a double-exponential rate: the classical cost of simulating a quantum circuit increases exponentially with computational volume, and hardware improvements will probably follow a quantum-processor equivalent of Moore’s law, doubling this computational volume every few years. To sustain the double-exponential growth rate and to eventually offer the computational volume needed to run well known quantum algorithms, such as the Shor or Grover algorithms, the engineering of quantum error correction will need to become a focus of attention.

未来

基于超导量子比特的量子处理器现在可以在维度为253 ≈ 9 × 10^15的希尔伯特空间中执行计算，超出了今天最快的经典超级计算机的能力。据我们所知，这个实验标志着只能在量子处理器上执行的第一次计算。量子处理器因此达到了量子优势的领域。我们预计它们的计算能力将继续以双指数速率增长：模拟量子电路的经典成本随着计算量的增加而指数级增长，而硬件改进可能会遵循量子处理器的摩尔定律，每几年将计算量翻倍。为了维持双指数增长率，并最终提供运行著名量子算法（如Shor或Grover算法）所需的计算量，量子错误纠正的工程化将需要成为关注的焦点。

The extended Church–Turing thesis formulated by Bernstein and Vazirani asserts that any ‘reasonable’ model of computation can be efficiently simulated by a Turing machine. Our experiment suggests that a model of computation may now be available that violates this assertion. We have performed random quantum circuit sampling in polynomial time using a physically realizable quantum processor (with sufficiently low error rates), yet no efficient method is known to exist for classical computing machinery. As a result of these developments, quantum computing is transitioning from a research topic to a technology that unlocks new computational capabilities. We are only one creative algorithm away from valuable near-term applications.

伯恩斯坦和瓦齐拉尼提出的扩展丘奇-图灵论断言，任何“合理”的计算模型都可以被图灵机高效模拟。我们的实验表明，现在可能有一个计算模型可以违反这一论断。我们已经使用物理上可实现的量子处理器（具有足够低的错误率）在多项式时间内执行了随机量子电路采样，但尚无已知的高效方法适用于经典计算机。因此，随着这些发展的推进，量子计算正在从一个研究主题转变为一种解锁新计算能力的技术。我们距离有价值的短期应用只差一个创造性的算法。