DDS信号发生器原理：

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2024/09/04 15:20:30
// Design Name: hilary
// Module Name: DDS_Module
//module DDS_Module(Clk,Reset_n,Fword,Pword,Data);input Clk;input Reset_n;input [31:0] Fword;input [11:0] Pword;output [13:0] Data;//频率控制字的同步寄存器reg [31:0] Fword_r ;always@(posedge Clk)Fword_r <= Fword ;//相位控制字的同步寄存器reg [31:0] Pword_r ;always@(posedge Clk)Pword_r <= Pword ;        //相位累加寄存器reg [31:0] Freq_ACC;always@(posedge Clk or negedge Reset_n)if(!Reset_n)Freq_ACC <= 0  ;elseFreq_ACC <= Fword_r + Freq_ACC ;//波形数据表地址        wire [11:0] Rom_Addr;assign Rom_Addr = Freq_ACC[31:20] + Pword_r;rom rom(.clka(Clk),.addra(Rom_Addr),.douta(Data));endmodule

`timescale 1ns / 1psmodule DDS_Module_tb;reg Clk;reg Reset_n;reg [31:0] FwordA,FwordB;reg[11:0] PwordA,PwordB;wire [13:0] DataA,DataB;DDS_Module DDS_ModuleA(Clk,Reset_n,FwordA,PwordA,DataA      );DDS_Module DDS_ModuleB(Clk,Reset_n,FwordB,PwordB,DataB        );       initial Clk = 1;always#10 Clk = ~Clk;initial beginReset_n = 0;FwordA = 65536;PwordA = 0;FwordB = 65536;PwordB = 1024;#201;Reset_n = 1;#5000000;FwordA = 65536*1024;FwordB = 65536*1024;PwordA = 0;PwordB = 2048;#1000000;$stop;end
endmodule