英伟达NVIDIA数字IC后端笔试真题（ASIC Physical Design Engineer）

今天小编给大家分享下英伟达NVIDIA近两年数字IC后端笔试真题（ASIC Physical Design）

请使用OR门和INV反相器来搭建下面所示F逻辑表达式的电路图。

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数字IC后端设计如何从零基础快速入门？(内附数字IC后端学习视频）

2024届IC秋招兆易创新数字IC后端笔试面试题

异步复位&同步复位

What is synchronous reset and asynchronous reset?
Please list at least 1 disadvantage each for synchronous and asynchronous reset respectively. How to resolve these issues? How to solve these issues?

Synchronous reset means reset is sampled with respect to clock. In other words, when reset is enabled, it will not be effective until the next active clock edge.
In asynchronous reset, reset is sampled independent of clk. That means, when reset is enabled it will be effective immediately and will not check or wait for the active clock edges.
2) Disadvantages of synchronous reset

Reset signal needs to be stretched, if it is not long enough to be seen at the active clock edge.
Requires a clock to be present if reset is to occur
If there are internal tri-state buffers, separate asynchronous reset may still be required
If there are gated clocks for power saving, this type of reset is not suitable.
Synthesis will not be able to easily differentiate reset from other signals. So this has to be taken care while doing synthesis. Otherwise it may lead to timing issues.
3) Disadvantages of asynchronous reset

Reset line is sensitive to glitches.
There may be metastability issues in the circuits.
4) Solution

Asynchronous reset and synchronous release（异步复位同步释放）.

数字后端名词解释

Please briefly describe below terminologies in digital circuit design：combination logic, gray code, metastability, lockup latch，setup, static power, logic synthesis, time borrow, power gating, process variation

combinational logic: A type of digital logic implemented by Boolean circuit, where the output is a pure function of the present input only. Combinational logic does not require clock to realize the function.
gray code: Gray code is an ordering of the binary numeral system such that two successive values differ in only one bit.
metastability: States where the signals can settle to an intermediate value between logic 0 and logic 1, this is called metastable state.
lockup latch: A lockup latch is a transparent latch used to avoid large clock skew and mitigate the problem in closing hold timing due to large uncommon clock path. Lockup latch is an important element in scan-based designs, especially for hold timing closure of shift modes. Lockup latches are necessary to avoid skew problems during shift phase of scan-based testing.

吾爱IC：原来负沿Latch可以用来修hold（Timing borrowing及其应用）
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setup: The setup time is the time during which a data signal must remain stable before the active clock edge.
static power: Power consumption caused by leakage currents including sub-threshold leakage, gate leakage, gate induced drain leakage, reverse bias junction leakage.
logic synthesis: The process of converting a functional behavioral model of a system represented as RTL model to structural (logical gate netlist) description model is called logic synthesis. It is a process of creating logic circuit from circuit description.
time borrow: Time borrow, also called cycle stealing, occurs at a latch. Since a latch is transparent when the clock is active, the data can arrive later than the active clock edge, that is, it can borrow time from the next cycle.
power gating: Shut down the power supply to a block of logic when it is not active.

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process variation: Operating conditions like process, temperature, and voltage define the process variations, which affect the functionality and performance of the SOC design.

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11）Please briefly introduce what is physical synthesis. What are the benefits compared with logical only synthesis? （考查逻辑综合和物理综合基本概念和各自的优缺点）

4.利用脚本处理文件
There is a file named “scores.txt” which has below format: name score. Please read this file and print out the passing list (score >= 60) & the failing list (score < 60), both list ranking by scores from highest to lowest. You can use Perl/Tcl/Python/C to implement the code.
File scores.txt:

Joe 90

Tom 58

Jim 70

James 95

Alan 82

John 89

Mike 85

Sandy 55

Nancy 88

Sherry 72

Alice 80

Tony 60

脚本处理题记得借助chatGPT来完成。

open IN,'<','scores.txt';
my %passing_list,%failing_list;
while(<IN>){if(/(\w+)\s+(\d+)/){$name = $1;$score = $2;if($score>=60){$passing_list{$name} = $score;}if($score<60){$failing_list{$name} = $score;}}
}
print "Passing list:\n";
foreach $key (sort {$passing_list{$b} <=> $passing_list{$a}} keys %passing_list){print "\t$key\t$passing_list{$key}\n";
};
print "\n";
print "Failing list:\n";
foreach $key (sort {$failing_list{$b} <=> $failing_list{$a}} keys %failing_list){print "\t$key\t$failing_list{$key}\n";
};   
close IN;

英伟达Nvidia几乎每年都会考到利用tcl等脚本语言来处理文本文件。

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5.crosstalk知识点考查

Below figure shows a circuit that include cross-coupled capacitances. Please answer the following questions: 1) The waveforms on A, B and clk are shown as below. Considering the impact of crosstalk, please draw the waveform on pin D. And analyze the timing impact on pin D under below condition. 2) Please list at least 3 methods to reduce the impact of crosstalk and analyze its disadvantage.

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1)Considering the impact of crosstalk, the transition time of signal on D pin will be reduced compared with waveform on B. This is because aggressor switching (net a) in same direction can result in a smaller delay for the switching net b.

2)if required, shielding wires between the nets, with Vdd and Vss nets to be run between two parallel long nets.（Disadvantages: shielding consumes more power, increases routing area and add interconnect complexity.）

not to run two long parallel interconnects on the same layer（Disadvantages: add interconnect complexity.)
increase spacing of parallel interconnect nets ( Disadvantages: need more routing resources and may increase die area.)
increase drive of victim net and decease drive of aggressor net.
use different routing layers (Disadvantages: need more routing resources.)

6.时序计算题

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